Text

Design of an IEEE compliant 32-bit floating point multiplier/accumulator

About this Digital Document

Full Title
Design of an IEEE compliant 32-bit floating point multiplier/accumulator
Member of
Theses and Dissertations
Contributor(s)
Creator: Niescier, Richard J.
Thesis advisor: Li, Weiping
Publisher
Lehigh University
Date Issued
1994-05
Language
English
Type
Text
Genre
theses
Form
electronic documents
Department name
Electrical Engineering and Computer Science
Digital Format
electronic documents
Media type
application/pdf
Creator role
Graduate Student
Identifier
31429694
https://asa.lib.lehigh.edu/Record/407824
Keywords
Computers
Electrical engineering
Niescier, . R. J. (1994). Design of an IEEE compliant 32-bit floating point multiplier/accumulator (1–). https://preserve.lehigh.edu/lehigh-scholarship/graduate-publications-theses-dissertations/theses-dissertations/design-ieee
Niescier, Richard J. 1994. “Design of an IEEE Compliant 32-Bit Floating Point Multiplier Accumulator”. https://preserve.lehigh.edu/lehigh-scholarship/graduate-publications-theses-dissertations/theses-dissertations/design-ieee.
Niescier, Richard J. Design of an IEEE Compliant 32-Bit Floating Point Multiplier Accumulator. May 1994, https://preserve.lehigh.edu/lehigh-scholarship/graduate-publications-theses-dissertations/theses-dissertations/design-ieee.