Doctor of Philosophy
James C. Hwang
For the last 50 years, Si metal-oxide-semiconductor field-effect transistors (MOSFETs) have undergone tremendous development under the Moore’s law. However, it has become more and more difficult to continue the scaling due to the limitation of Si quantum confinement when the gate length is less than 5 nm.
Two-dimensional (2D) atomic-layered materials may replace Si in future-generation ultra-thin-body, low-power, and high-performance MOSFETs. However, for any 2D material to replace Si, it must not only have high mobility and sizable bandgap, but also be manufacturable. Graphene has high mobility but no bandgap. MoS2 has sizable bandgap but low mobility. Black phosphorus (BP) has high mobility and sizable bandgap but is unstable in air and has not been grown under reasonable pressure and temperature. By contrast, monolayer PtSe2 has high mobility, sizable bandgap, air stability, and can be synthesized below 450 °C ‒ −the thermal budget of CMOS back-of-the-line (BEOL) processes (BEOL). Additionally, bulk PtSe2 is semi-metallic to facilitate low resistance contact, a critical issue for all 2D devices. Experimentally, PtSe2 MOSFETs have been demonstrated by exfoliated flakes, chemical vapor deposited film, and thermal assisted converted film.
In this dissertation, both material preparation and device fabrication are done below 450 °C. Transistors based on molecular beam epitaxy grown PtSe2 are fabricated and characterized for the first time. With 3-monolayer (ML) PtSe2 grown by molecular beam, transistor with n-type carrier has been demonstrated with on/off ratio of 43, which increases to 1600 at 80 K and is the best among n-type PtSe2 transistors fabricated on grown films.
The MOSFETs are batch-fabricated by a CMOS-compatible process based on 200-mm-diameter Si substrates prepared by a state-of-the-art BiCMOS foundry. Dozens of rounds of fabrication were carried out to ensure the yield of large-scale fabrication. Photoresist residue formed on 2D material were reduced by reduced dry etching time. The poor adhesion between 2D material and the substrate was also addressed.
Despite the thin PtSe2 layer, doping by contact bias lowers the contact resistance significantly and boosts the on current and on/off ratio. Temperature-dependent current-voltage characteristics show the bandgap is approximately 0.2 eV, which confirms that the semiconductor-semimetal transition of PtSe2 is not as abrupt as originally predicted.
By the chip maps, performances of 66 devices are presented, which show reasonable uniformity across the 10 mm × 10 mm chip.
Better MOSFET performance can be expected by growing even thinner PtSe2 uniformly and by thickening the PtSe2 in the contact regions.
Xiong, Kuanchen, "Design, Fabrication, Characterization and Modeling of CMOS-Compatible PtSe2 MOSFETs" (2020). Theses and Dissertations. 5713.