Master of Science
Hardware prefetching is an efficient way to hide cache miss penalty due to long memory access latency. Accuracy, coverage, and timeliness are three primary metrics in evaluating hardware prefetcher design. Highly accurate hardware prefetches are required to predict complex memory access patterns in multicore systems. In this paper, we propose a long short term memory (LSTM) prefetcher---a neural network based hardware prefetcher to achieve high prefetch accuracy and coverage while improving prefetch timeliness. The proposed LSTM prefetcher achieves higher accuracy and coverage by training neural networks to predict long memory access patterns. LSTM can improve timeliness in two approaches. First, multiple prefetch can be issued on a single cache access. Second, a simple Next-N-Line prefetcher is integrated with the LSTM prefetcher to accelerate predictions when good spatial locality exists. The proposed LSTM prefetcher is the first prefetcher design that uses recurrent neuron network. Three case studies are presented, which show that proposed LSTM prefetcher can achieve 98.6\%, 83.5\%, and 61\% accuracy respectively, while the state-of-art variable length delta prefetcher (VLDP) achieves 0\%, 75\% ,and 26.6\% accuracy in predicting the sequences in the case studies.
Zeng, Yuan, "Long Short Term Based Memory Hardware Prefetcher" (2017). Theses and Dissertations. 2901.
Available for download on Wednesday, June 06, 2018